1. Field of the Invention
The present invention is generally related to general purpose, stored program, digital computers and more particularly relates to efficient architectures having a capability to automatically reconfigure in the event a fault is detected to improve reliability.
2. Description of the Prior Art
A key element in the design of digital data processing equipment is the factor of reliability. One technique for the enhancement of reliability is the use of internally redundant components. U.S. Pat. Nos. 4,551,814 and 4,551,815, issued to Moore et al. describe an approach to internally redundant individual logic elements. This technique is extremely costly, however. Furthermore, reliability at the system level must ultimately be addressed as a system design problem, because system reliability concerns more than just the sum of the reliability of the components.
One field in which substantial effort has been expended towards system level reliability is in telephone switching networks. U.S. Pat. No. 4,625,081, issued to Lotito et al. describes a large scale modern telephone switching network. A non-blocking packet switching network having some capability to automatically switch into non-blocking configurations is discussed in U.S. Pat. No. 4,696,000, issued to Payne, III. A method and apparatus for rerouting of telephone data for the improvement of reliability is suggested in U.S. Pat. No. 4,649,384, issued to Sheafor et al.
U.S. Pat. No. 4,074,072, issued to Christiansen et al., shows a switching network which operates under multiprocessor control. Fast packet switching is discussed in U.S. Pat. Nos. 4,491,945 and 4,494,230, both issued to Turner. Alternative packet switching systems are shown in U.S. Pat. No. 4,872,159, issued to Hemmady et al. and U.S. Pat. No. 4,679,186, issued to Lea. A measure of improved reliability is provided by redundant resources in the Lea approach.
Digital tone distribution is provided by the network of U.S. Pat. No. 4,480,330, issued to Magnusson et al., whereas U.S. Pat. No. 5,163,087, issued to Kaplan shows a network which converts an automatic number identification into a customer data base key.
An architecture for a high speed packet switching network is discussed in U.S. Pat. No. 4,899,333, issued to Roediger. An alternative high speed routing approach is shown in U.S. Pat. No. 5,038,343, issued to Lebizay et al. Yet another approach to self-routing is seen in U.S. Pat. No. 4,864,558, issued to Imagawa et al. U.S. Pat. No. 5,161,156, issued to Baum et al. provides an approach to a high speed packet switching network having an error correction and recovery capability. An optical network is shown in U.S. Pat. No. 5,005,167, issued to Arthurs et al. A self-routing packet switching network is discussed in U.S. Pat. No. 4,899,335, issued to Johnson, Jr. et al. U.S. Pat. No. 5,130,982, issued to Ash et al., provides a fully shared communications network.
The problems associated with data transmission within a data processing system tend to be exacerbated by the higher speeds involved. A common architectural approach uses a common shared bus for the transmission of digital data to control the cost of the transmitting and receiving resources. U.S. Pat. No. 5,051,742, issued to Hullett et al., describes a queuing protocol for a system employing a bussed architecture. U.S. Pat. No. 4,794,594, issued to Picard, uses a common bus for transfer of data blocks within a communications network. A modularized approach to communication within a bussed architecture is found in U.S. Pat. No. 4,365,294, issued to Stokken. U.S. Pat. No. 5,163,131, issued to Row et al., provides a file server architecture using a common shared bus.
The vector processor of U.S. Pat. No. 4,621,339, issued to Wagner et al., provides parallel processing through the use of a single instruction-multiple data (SIMD) architecture. A similar vector processing architecture is seen in U.S. Pat. No. 4,891,751, issued to Call et al.
The use of bussed architectures, while efficiently employing the interconnect elements, presents reliability problems, since the bus is a shared component subject to preventing any and all intra-system communication upon failure. One approach to improving reliability within a bussed architecture involves taking particular precautions with those circuits which directly interact with the bus. U.S. Pat. No. 4,556,939, issued to Read, provides interface circuits which are called highways to couple with the bus. A measure of added bus reliability is thus obtained through the use of redundancy within the highway interfaces.
An alternative approach to the reliability problem is through the use of point-to-point rather than bussed architectures. These tend to be quite costly because of the greater amount of hardware required. As a result, such techniques are primarily employed for input/output transfers wherein the added hardware may be required anyway because of the physical separation of the communicating elements. U.S. Pat. No. 4,562,533, issued to Hodel et al., shows such an input/output transmission system.
An intermediate alternative between the totally shared common bus and the point-to-point approach may be seen in U.S. Pat. No. 5,041,971, issued to Carvey et al., which routes the data using switching elements, through which a transmission path may be selected. Reliability is improved because multiple independent paths may be configured for transmission of data between any two system elements. To ensure that the switching system is non-blocking, enough paths are provided to permit simultaneous communication between any and all combinations of system elements. In part to mitigate the extreme cost of this approach, only synchronous serial transmissions are provided. This greatly decreases the effective bandpass in comparison to systems employing wide word (i.e. 32 or more bits) parallel transfers for intra-system data transmissions.